1. Field of the Invention
The invention relates generally to a semiconductor device and a method of manufacturing the same and, more particularly, to a method of forming a buried insulation film in a bulk silicon wafer and a semiconductor device manufactured using the method.
2. Description of the Related Art
As processes of manufacturing semiconductor devices are finely controlled, there are many technical difficulties in manufacturing Dynamic Random Access Memory (DRAM) having a unit memory cell composed of one transistor and one capacitor. Among the technical difficulties, it is most difficult to improve short channel effect characteristics while simultaneously maintaining sufficient data retention time, and to minimize dielectric loss characteristics in a narrow area while simultaneously fabricating a capacitor having sufficient capacitance. In particular, the technology of fabricating a capacitor which has sufficient capacitance necessary for the operation of DRAM and which can ensure reliability is subject to a technical limitation, and is a very difficult process technology. In order to solve such a problem, wide-ranging research into 1 T DRAM using a floating body effect of a transistor has been made. (1 T DRAM is a “capacitorless” bit cell design that stores data in the parasitic body capacitor that is an inherent part of silicon-on-insulator (SOI) transistors.)
Meanwhile, conventional 1 T-1 C DRAM (“one transistor, one capacitor” DRAM) stores electric charges in a capacitor, whereas 1 T DRAM is used as memory because threshold voltage changes when electric charges are stored in the body of a transistor. Generally, a transistor constituting a memory cell of 1 T DRAM is fabricated using a silicon-on-insulator (SOI) wafer. However, since SOI wafers are expensive, economical efficiency is low. Further, an external circuit for operating a memory cell of 1 T DRAM must also be provided on the SOI wafer.
In order to overcome the low economical efficiency of the SOI wafer, a method of manufacturing 1 T DRAM using a bulk silicon wafer is proposed. In this method, in order to realize a floating body cell, a P-type well is formed in a deep N-type well to cause a floating body to be floated. However, in such a method, since a bulk silicon wafer is used instead of the expensive SOI wafer, economical efficiency can be relatively improved, but sufficient data retention time cannot be ensured due to leakage current generated from the interface between the N-type well and the P-type well.